The present invention relates to a counter circuit. More particularly, the present invention pertains to an improved counter circuit that may be operated at faster frequencies and reduce power consumption.
Counter circuits are generally known in the art. A counter typically includes a number of identical stages where each stage outputs one binary digit of the count. For example, a 10 bit ripple counter is able to count from binary 0 to binary 1023 and includes 10 identical stages. The 10-bit ripple counter, as a whole, will include one input for a clocking signal so that the counter will increment or decrement by one binary digit for each period of the clocking signal. For example, the counter may increment/decrement on each falling edge of the clocking signal. For an incrementing ripple counter, the first stage receives a clocking input, which is provided to the clock input of a J-K flip-flop while the J and K inputs are tied to a high voltage (i.e., binary xe2x80x9c1xe2x80x9d) value. When the clocking signal reaches a falling edge, the first JK flip-flop would transition from a xe2x80x9c0xe2x80x9d value to a xe2x80x9c1xe2x80x9d value if this xe2x80x9cstagexe2x80x9d has been cleared prior to operation. The output of the first J-K flip-flop is the least significant bit (LSB) of the counter and is supplied as the clocking input of the second J-K flip-flop. On the next clocking signal, the output of the first flip-flop will drop to xe2x80x9c0xe2x80x9d and will cause the output of the second J-K flip-flop to rise to a xe2x80x9c1xe2x80x9d value if this stage has been cleared prior to operation. In a 10 bit ripple counter, there would be 10 such J-K flip-flops coupled in much the same manner. The output of the tenth J-K flip-flop would be the most significant bit (MSB) and the 10 outputs of the 10 J-K flip-flops will represent the number of falling edges of the clocking signal received by the first J-K flip-flop.
Problems seen with a counter of this type concern how this counter reaches its final value and is reset to its initial value. To determine if the counter has reached its final value a string of AND gates are typically used, for example, to compare the output bit for each stage to the value xe2x80x9c1.xe2x80x9d Once all of the stages have been set to xe2x80x9c1xe2x80x9d in this example, the stages must then be reset to an initial value. The more stages included in the counter, the longer these two steps take. If the counter is being used in a divider circuit (e.g., to convert a clocking signal into one have a lower frequency), the resetting of all of the stages must occur during one period of the original clocking signal. As clocking signals become faster and faster, such procedures become more difficult. Furthermore, the toggling of signals at the outputs of comparators (e.g., AND gates) and counter stages may make the counter power inefficient.